At the deep sub-micron level, such as 90 nm or 65 nm structures, the protection of transistor gates has become important. One example of a design rule in deep sub-micron technologies is that the gate voltage should not be larger than the supply voltage of a transistor. In an application specific integrated circuit (ASIC) design, thousands of gates and/or pins are each connected either to a static “logic one” or “logic zero” The gate and/or pins need to be connected to a voltage VDD or a voltage VSS. The voltage VDD or VSS is connected to the gate of the transistors. This approach is called “tie up” or “tie down” of a signal and/or gate.
Conventional tie up and tie down nets generally provide one of the largest contributions to high fanout “signal” nets in designs. In 90 nm or 65 nm technologies, design rules generally prohibit the voltage at a gate from being larger than the voltage for the supply of the transistor. With conventional methods, the gate input of the transistor is tied to the logic zero and/or the logic one. A cell power rail and/or a thick power rail is directly connected to the gate input of a transistor. The transistor is tied to the logic zero and/or logic one. Conventional approaches cannot assure that the gate input voltage of the transistor is lower than the voltage of the power supply.
Conventional approaches attempt to solve this issue by inserting an electrostatic discharge (ESD) buffer and/or decoupling buffer to avoid the direct connection of the logic gate to the VDD or VSS net. The inserted buffer is a global cell that connects global signals. The buffer is manually inserted in the netlist. The manual connection is made by the designer.
Referring to FIG. 1, a block diagram of a circuit 10 illustrating a conventional approach for connecting one or more standard cells is shown. The circuit 10 generally comprises a number of I/O cells 12a-12n, a global tie down cell 14, a global tie up cell 16, a number of standard cells 18a-18n, and a number of standard cells 20a-20n. The standard cells 18a-18n are coupled to the global tie down cell 14. The global tie down cell 14 is coupled to the I/O cell 12c. The voltage VSS is supplied to the I/O cell 12c. The standard cells 20a-20n are coupled to the global tie up cell 16. The global tie up cell 16 is coupled to the I/O cell 12b. The voltage VDD is supplied to the I/O cell 12b. 
With the circuit 10, only one global tie up cell 14 and one global tie down cell 16 are implemented. The single global tie up cell 16 and the single global tie down cell 14 do not link to the real design. The global tie down cell 14 and tie up cell 16 generate interconnect signals that can be the root cause of many issues in the subsequent design flow. The global tie down cell 14 and tie up cell 16 can significantly hurt the design closure flow by generating severe congestion during the design routing phase.